Operation; Fifo - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
22.5

Operation

22.5.1

FIFO

31
0
Figure 22-12 Transmission FIFO buffer
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
(1) Transmission FIFO buffer
When the IEBBnTMS.IEBBnFMDE bit = 1, data can be stored in the FIFO buffer
while automatically incrementing the FIFO buffer pointer for writing by continuously
writing transmission data to the IEBBnDR register. The FIFO buffer size is 8 bits x 32
stages.
When the transfer is started, the data indicated by the load pointer is transferred. After
the transfer finishes, the load pointer is incremented. The initial value for the write
pointer and load pointer is 0.
The IEBBnBSR.IEBBnTFLF bit is set (to 1) when there are 32 bytes of data in the
FIFO buffer, and the transmission FIFO buffer overwrite flag
(IEBBnBSR.IEBBnFOVW) is set (to 1) when a 33rd byte of data is written while the
IEBBnTFLF bit = 1. At this time, the write data is ignored and the write pointer is not
changed.
The data below can be written when one byte is transferred while the IEBBnTFLF bit
= 1 and then the bit is cleared to 0.
If the write is not in time for data loading, an underrun error occurs.
7
Transmission FIFO buffer
0
Write pointer
Load pointer
22. IEBus Controller
22-79