Line Status Register (Sclsr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
14.3.12

Line Status Register (SCLSR)

The CPU can always read or write to SCLSR, but cannot write 1 to the ORER flag. This flag can be cleared to 0 only if it
has first been read (after being set to 1).
Bit: 15
-
Initial value: 0
R/W: R
Note: * Only 0 can be written to clear the flag after 1 is read.
Bit Bit Name
—
15 to 1
0 ORER
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0 R/(W)* Overrun Error
Indicates the occurrence of an overrun error during reception.
0: Receiving is in progress or has ended normally*
[Clearing conditions]
• ORER is cleared to 0 by a power-on reset
• ORER is cleared to 0 when 0 is written after 1 is read from ORER.
1: An overrun error has occurred during reception*
[Setting condition]
• ORER is set to 1 when the next serial receiving is finished while the receive
FIFO is full of 16-byte receive data.
Note: 1. Clearing the RE bit to 0 in SCSCR does not affect the ORER bit, which
14. Serial Communication Interface with FIFO
9 8 7 6 5
- - - - -
0 0 0 0 0
R R R R R
retains its previous value.
2. The receive FIFO data register (SCFRDR) retains the data before
an overrun error has occurred, and the next received data is
discarded. When the ORER bit is set to 1, the next serial
reception cannot be continued.
4 3 2 1 0
- - - - ORER
0 0 0 0 0
R R R R R/(W)*
1
2
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