Rscan0Cmcfg - Channel Configuration Register (M = 0 Or 1) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.1 RSCAN0CmCFG — Channel Configuration Register (m = 0 or 1)
Access: Can be read/written in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 0000
Initial value: 0000 0000
H
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 21.15
Bit Position
31 to 26
25, 24
23
22 to 20
19 to 16
15 to 10
9 to 0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
+ (m * 0010 )
H H
28 27 26 25
— — — SJW[1:0]
0 0 0 0
R R R R/W
12 11 10 9
— — —
0 0 0 0
R R R R/W
RSCAN0CmCFG register contents
Bit Name Function
Reserved These bits are always read as 0. The write value should always be 0.
SJW[1:0] Resynchronization Jump Width Control
b25 b24
0 0: 1 Tq
0 1: 2 Tq
1 0: 3 Tq
1 1: 4 Tq
Reserved This bit is always read as 0. The write value should always be 0.
TSEG2[2:0] Time Segment 2 Control
b22 b21 b20
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
TSEG1[3:0] Time Segment 1 Control
b19 b18 b17 b16
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
Reserved These bits are always read as 0. The write value should always be 0.
BRP[9:0] Prescaler Division Ratio Set
When these bits are set to P (0 to 1023), the baud rate prescaler divides fCAN
by P + 1.
24 23 22 21
— TSEG2[2:0]
0 0 0 0
R/W R R/W R/W
8 7 6 5
BRP[9:0]
0 0 0 0
R/W R/W R/W R/W
0: Setting prohibited
1: 2 Tq
0: 3 Tq
1: 4 Tq
0: 5 Tq
1: 6 Tq
0: 7 Tq
1: 8 Tq
0 0: Setting prohibited
0 1: Setting prohibited
1 0: Setting prohibited
1 1: 4 Tq
0 0: 5 Tq
0 1: 6 Tq
1 0: 7 Tq
1 1: 8 Tq
0 0: 9 Tq
0 1: 10 Tq
1 0: 11 Tq
1 1: 12 Tq
0 0: 13 Tq
0 1: 14 Tq
1 0: 15 Tq
1 1: 16 Tq
21. CAN Interface
20 19 18 17
TSEG1[3:0]
0 0 0 0
R/W R/W R/W R/W
4 3 2 1
0 0 0 0
R/W R/W R/W R/W
16
0
R/W
0
0
R/W
21-20