Initialization - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
(2) Mode Fault Error
When the MSTR bit is 0, this module operates in slave mode. This module detects a mode fault error if the SSL input
signal is negated during the serial transfer period (from the time the driving of valid data is started to the time the final
valid data is fetched) when the MODFEN bit is 1 in slave mode.
Upon detecting a mode fault error, this module stops driving of the output signals and clears the SPE bit in SPCR to 0.
When the SPE bit is cleared to 0, the function of this module is disabled and this module stops driving external signals.
For details of disabling the function of this module by clearing the SPE bit to 0, see section 16.4.7, Initialization.
The occurrence of a mode fault error can be checked either by reading SPSR or by using an error interrupt and reading
SPSR. When using an error interrupt, set the SPEIE bit in the control register (SPCR) to 1. To detect a mode fault error
without using an error interrupt, it is necessary to poll SPSR.
When the MODF bit is 1, writing 1 to the SPE bit is ignored. To enable the function of this module after the detection of
a mode fault error, the MODF bit must be set to 0. The MODF bit is cleared to 0 under the following conditions:
• After SPSR is read in a condition where the MODF bit has turned 1, 0 is written to the MODF bit.
• Power-on reset
16.4.7

Initialization

If 0 is written to the SPE bit in the control register (SPCR) or this module clears the SPE bit to 0 because of the detection
of a mode fault error, this module disables the module function, and initializes a part of the module function. When a
power-on reset is generated, this module initializes all of the module function. An explanation follows of initialization by
the clearing of the SPE bit.
(1) Initialization by Clearing SPE Bit
When the SPE bit in SPCR is cleared, this module performs the following initialization:
• Suspending any serial transfer that is being executed
• Stopping the driving of output signals (Hi-Z) in slave mode
• Initializing the internal state
• Initializing the TEND bit in SPSR
Initialization by the clearing of the SPE bit does not initialize the control bits of this module. For this reason, this module
can be started in the same transfer mode as prior to the initialization if the SPE bit is re-set to 1.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
16. Renesas Serial Peripheral Interface
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