Fifo Data Count Set Register (Scfdr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
14.3.10

FIFO Data Count Set Register (SCFDR)

SCFDR is a 16-bit register which indicates the quantity of data stored in the transmit FIFO data register (SCFTDR) and
the receive FIFO data register (SCFRDR).
It indicates the quantity of transmit data in SCFTDR with the upper 8 bits, and the quantity of receive data in SCFRDR
with the lower 8 bits. SCFDR can always be read by the CPU.
Bit: 15
-
Initial value: 0
R/W: R
Bit Bit Name
—
15 to 13
12 to 8 T[4:0]
—
7 to 5
4 to 0 R[4:0]
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
14 13 12 11 10
- - T[4:0]
0 0 0 0 0
R R R R R
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
00000 R T4 to T0 bits indicate the quantity of non-transmitted data stored in SCFTDR.
H'00 means no transmit data, and H'10 means that all transmit data is stored in
SCFTDR.
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
00000 R R4 to R0 bits indicate the quantity of receive data stored in SCFRDR. H'00
means no receive data, and H'10 means that all receive data is stored in
SCFRDR.
14. Serial Communication Interface with FIFO
9 8 7 6 5
- - -
0 0 0 0 0
R R R R R
4 3 2 1 0
R[4:0]
0 0 0 0 0
R R R R R
14-21