Buffer Operation - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.4.3

Buffer Operation

Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. In channel
0, TGRF can also be used as a buffer register.
Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare
match register.
Note: TGRE_0 cannot be designated as an input capture register and can only operate as a compare match register.
Table 10.41 shows the register combinations used in buffer operation.
Table 10.41 Register Combinations in Buffer Operation
Channel
0
3
4
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the
timer general register.
This operation is illustrated in Figure 10.14.
Figure 10.14 Compare Match Buffer Operation
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer
general register is transferred to the buffer register.
This operation is illustrated in Figure 10.15.
Figure 10.15 Input Capture Buffer Operation
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Timer General Register
TGRA_0
TGRB_0
TGRE_0
TGRA_3
TGRB_3
TGRA_4
TGRB_4
Compare match signal
Buffer Timer general
register register
Input capture
signal
Buffer Timer general
register
10. Multi-Function Timer Pulse Unit 2
Buffer Register
TGRC_0
TGRD_0
TGRF_0
TGRC_3
TGRD_3
TGRC_4
TGRD_4
Comparator
register
TCNT
TCNT
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