Boot Mode 1 - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
3.5 Operation
3.5.1 Boot Mode 0
In boot mode 0, this LSI is booted from the memory connected to the CS0 space. In these modes, this LSI operates as
follows:
After the power-on reset is canceled, program execution is started from H'0000_0000 in the memory connected to the
CS0 space.
3.5.2

Boot Mode 1

In boot mode 1, booting up is from the serial flash memory connected to the SPI multi I/O bus space. In this mode, this
LSI operates as follows: After the power-on reset is canceled, the boot program stored in the on-chip ROM (starting from
H'FFFF_0000) is executed.
The boot program configures the SPI multi I/O bus controller in external address space read mode. With this
configuration, this LSI converts reads from the SPI multi I/O bus space to SPI communications and is ready to read
directly from the connected serial flash memory. The boot program configures a read command (opcode: 03H, address: 3
bytes, dummy cycle: none) as the command to the serial flash memory used for SPI communication conversion. Figure
3.1 shows the control signals output to the serial flash memory through SPI communication conversion.
SPBSSL_0
SPBCLK_0
SPBMO0_0
SPBMI0_0
Figure 3.1 Control Signals Output to the Serial Flash Memory Through SPI Communication Conversion
The boot program uses the area at H'2002_0000 to H'2002_3FFF as work memory. It branches to H'1800_0000 (SPI
multi I/O bus space) at the end of the processing. At this time, the I bit, F bit, T bit and bits Mode[4:0] in CPSR are set to
the initial states with the I bit set to 1'b1 (IRQ masked state), the F bit set to 1'b1 (FIQ masked state), the T bit set to 1'b0
(Arm state) and bits Mode[4:0] set to 5'b10011 (supervisor mode).
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Command Address
03H 3 bytes
Read data
8/16/32/64 bits
3. Boot Mode
3-4