RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.23
RSCAN0RFCCx — Receive FIFO Buffer Configuration and Control Register
(x = 0 to 7)
Access:
Can be read/written in 8-, 16-, and 32-bit units
Address:
<RSCAN0_base> + 00B8
Initial value:
0000 0000
Bit
31
30
29
—
—
—
Initial value
0
0
0
R/W
R
R
R
Bit
15
14
13
RFIGCV[2:0]
0
0
0
Initial value
R/W
R/W
R/W
R/W
Table 21.37
Bit Position
31 to 16
15 to 13
12
11
10 to 8
7 to 2
1
0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
+ (x * 0004
)
H
H
H
28
27
26
—
—
—
0
0
0
R
R
R
12
11
10
RFIM
—
RFDC[2:0]
0
0
0
R/W
R
R/W
RSCAN0RFCCx register contents
Bit Name
Function
Reserved
These bits are always read as 0. The write value should always be 0.
RFIGCV[2:0]
Receive FIFO Interrupt Request Timing Select
b15 b14 b13
RFIM
Receive FIFO Interrupt Source Select
Reserved
This bit is always read as 0. The write value should always be 0.
RFDC[2:0]
Receive FIFO Buffer Depth Configuration
b10 b9 b8
Reserved
These bits are always read as 0. The write value should always be 0.
RFIE
Receive FIFO Interrupt Enable
RFE
Receive FIFO Buffer Enable
25
24
23
22
—
—
—
—
0
0
0
0
R
R
R
R
9
8
7
6
—
—
0
0
0
0
R/W
R/W
R
R
0
0
0: When FIFO is 1/8 full.
0
0
1: When FIFO is 2/8 full.
0
1
0: When FIFO is 3/8 full.
0
1
1: When FIFO is 4/8 full.
1
0
0: When FIFO is 5/8 full.
1
0
1: When FIFO is 6/8 full.
1
1
0: When FIFO is 7/8 full.
1
1
1: When FIFO is full.
0: An interrupt occurs when the condition set by the RFIGCV[2:0] bits is met.
1: An interrupt occurs each time a message has been received.
0
0
0: 0 messages
0
0
1: 4 messages
0
1
0: 8 messages
0
1
1: 16 messages
1
0
0: 32 messages
1
0
1: 48 messages
1
1
0: 64 messages
1
1
1: 128 messages
0: Receive FIFO interrupt is disabled.
1: Receive FIFO interrupt is enabled.
0: No receive FIFO buffer is used.
1: Receive FIFO buffers are used.
21. CAN Interface
21
20
19
18
—
—
—
—
0
0
0
0
R
R
R
R
5
4
3
2
—
—
—
—
0
0
0
0
R
R
R
R
17
16
—
—
0
0
R
R
1
0
RFIE
RFE
0
0
R/W
R/W
21-57