Free-Running Comparison Mode - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
11.3.6

Free-Running Comparison Mode

11.3.6.1 Basic Operation in Free-Running Comparison Mode
In free-running comparison mode, the counter counts up from 0000 0000
OSTMnTINT interrupt request is output when the current value of the counter matches the value of the
OSTMnCMP register. The free-running comparison mode is selected by setting the
OSTMnCTL.OSTMnMD1 bit to 1.
New values can be written to the OSTMnCMP register at any time.
The following figure shows the basic operation of OSTM in free-run compare mode with the start of
counting enabled (OSTMnCTL.OSTMnMD0 = 1).
OSTMnTS
OSTMnTT
OSTMnTE
OSTMnCMP
OSTMnCNT
OSTMTINT
Figure 11.6
The timing diagram above shows the following:
(1) The counter starts counting when OSTMnTS.OSTMnTS = 1.
The OSTMnTE.OSTMnTE bit is set to indicate enabling of the counter. The counter counts up
from 0000 0000
current value.
When OSTMnCTL.OSTMnMD0 = 1, an OSTMTINT interrupt request is generated at the start of
counting.
(2) When the current counter value matches the value in the OSTMnCMP register, an OSTMTINT
interrupt request is generated.
(3) When the counter is stopped (OSTMnTT.OSTMnTT = 1), the OSTMnTE.OSTMnTE bit is
cleared to indicate disabling of the counter.
The counter retains its current value until it is restarted.
(4) Counting by the counter restarts from 0000 0000
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
A
FFFF FFFF
A
H
0000 0000
H
(a)
(1) (2)
Timing Diagram of OSTM in Free-Run Compare Mode
to FFFF FFFF . The OSTMnCNT register is the counter, so it contains the
H H
Counter operating
B C
A
B
(b) (c)
(2) (2)
when OSTMnTS.OSTMnTS = 1.
H
11. OS Timer
to FFFF FFFF . An
H H
D E
C
D
(d)
(2) (2) (3) (4)
E
(2)
11-13