Channel Interval Register N (Chitvl_N) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
Initial
Bit Bit Name Value
5 HIEN 0
4 LOEN 0
3 REQD 0
2 to 0 SEL[2:0] 000
9.4.10

Channel Interval Register n (CHITVL_n)

This register sets the transfer interval for DMA channel n (n = 0 to 15).
For details, see
section 9.7.9, Interval Count Function
Bit: 31
-
Initial value: 0
R/W: R
Bit: 15
0
Initial value:
R/W: R/W
Initial
Bit Bit Name Value
31 to 16 — All 0
15 to 0 ITVL All 0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
R/W Description
R/W High Enable
Selects whether to detect a DMA request using the High level or rising edge of the signal.
When LVL = 0:
HIEN = 1: Detects a request in response to the rising edge of the signal.
HIEN = 0: Does not detect a request in response to the rising edge of the signal (initial
value).
When LVL = 1:
HIEN = 1: Detects a request when the signal is at the High level.
HIEN = 0: Does not detect a request even when the signal is at the High level (initial value).
R/W Low Enable
Selects whether to detect a DMA request using the Low level or falling edge of the signal.
When LVL = 0:
LOEN = 1: Detects a request in response to the falling edge of the signal.
LOEN = 0: Does not detect a request in response to the falling edge of the signal (initial
value).
When LVL = 1:
LOEN = 1: Detects a request when the signal is at the Low level.
LOEN = 0: Does not detect a request even when the signal is at the Low level (initial value).
R/W Request Direction
Selects whether DMAREQ selected by the SEL bit is the source or destination. This bit is
also used to define when DMAACK is to become active.
0: Source; DMAACK is to become active when read (initial value).
1: Destination; DMAACK is to become active when written.
R/W These bits are used to set a DMAC channel. Set one of the following values so that the
channel set by the SEL bits matches the CHCFG_n channel.
000: CH0/CH8
001: CH1/CH9
010: CH2/CH10
011: CH3/CH11
100: CH4/CH12
101: CH5/CH13
110: CH6/CH14
111: CH7/CH15
.
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
0 0 0 0 0
R/W R/W R/W R/W R/W
R/W Description
R Reserved area. Set 0. A read operation results in 0 being read.
R/W Sets the channel transfer interval.
25 24 23 22 21
- - - - -
0 0 0 0 0
R R R R R
9 8 7 6 5
ITVL
0 0 0 0 0
R/W R/W R/W R/W R/W
9. Direct Memory Access Controller
20 19 18 17 16
- - - - -
0 0 0 0 0
R R R R R
4 3 2 1 0
0 0 0 0 0
R/W R/W R/W R/W R/W
9-22