64-Hz Counter (R64Cnt) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
13.3.1

64-Hz Counter (R64CNT)

R64CNT indicates the state of the divider circuit between 64 Hz and 1 Hz.
Reading this register, when carry from 128-Hz divider stage is generated, sets the CF bit in the control register 1 (RCR1)
to 1, which indicates that the carrying and reading the 64-Hz counter are performed at the same time. In this case, the
R64CNT should be read again after writing 0 to the CF bit in RCR1 since the read value is not valid.
Setting the RESET or ADJ bit in the control register 2 (RCR2) to 1 initializes the divider circuit and the R64CNT.
Bit Bit Name
—
7
6 1 Hz
5 2 Hz
4 4 Hz
3 8 Hz
2 16 Hz
1 32 Hz
0 64 Hz
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
BIt: 7 6
- 1Hz
Initial value: 0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W: R R
Initial
Value R/W Description
0 R Reserved
This bit is always read as 0. The write value should always be 0.
Undefined R Indicate the state of the divider circuit between 64 Hz and 1 Hz.
Undefined R
Undefined R
Undefined R
Undefined R
Undefined R
Undefined R
5 4 3 2 1
2Hz 4Hz 8Hz 16Hz 32Hz 64Hz
R R R R R
13. Realtime Clock
0
R
13-4