Serial Mode Register (Scsmr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
14.3.5

Serial Mode Register (SCSMR)

SCSMR specifies the serial communication format and selects the clock source for the baud rate generator.
The CPU can always read from and write to SCSMR.
Bit: 15
-
Initial value: 0
R/W: R
Bit Bit Name
—
15 to 8
7 C/A
6 CHR
5 PE
4 O/E
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0 R/W Communication Mode
Selects operating mode from asynchronous and clock synchronous modes.
0: Asynchronous mode
1: Clock synchronous mode
0 R/W Character Length
Selects 7-bit or 8-bit data length in asynchronous mode. In the clock
synchronous mode, the data length is always 8 bits, regardless of the CHR
setting.
0: 8-bit data
1: 7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit FIFO data
0 R/W Parity Enable
Selects whether to add a parity bit to transmit data and to check the parity of
receive data, in asynchronous mode. In clock synchronous mode, a parity bit is
neither added nor checked, regardless of the PE setting.
0: Parity bit not added or checked
1: Parity bit added and checked*
Note: * When PE is set to 1, an even or odd parity bit is added to transmit data,
0 R/W Parity Mode
Selects even or odd parity when parity bits are added and checked. The O/E
setting is used only in asynchronous mode and only when the parity enable bit
(PE) is set to 1 to enable parity addition and checking. The O/E setting is ignored
in clock synchronous mode or in asynchronous mode when parity addition and
checking is disabled.
0: Even parity*
1: Odd parity*
Note: 1. If even parity is selected, the parity bit is added to transmit data to make
14. Serial Communication Interface with FIFO
9 8 7 6 5
- - C/A CHR PE
0 0 0 0 0
R R R/W R/W R/W
register is not transmitted.
depending on the parity mode (O/E) setting. Receive data parity is
checked according to the even/odd (O/E) mode setting.
1
2
an even number of 1s in the transmitted character and parity bit
combined. Receive data is checked to see if it has an even number of
1s in the received character and parity bit combined.
2. If odd parity is selected, the parity bit is added to transmit data to
make an odd number of 1s in the transmitted character and parity
bit combined. Receive data is checked to see if it has an odd
number of 1s in the received character and parity bit combined.
4 3 2 1 0
O/E STOP - CKS[1:0]
0 0 0 0 0
R/W R/W R R/W R/W
14-7