Next Transaction Byte Register N (N0Tb_N, N1Tb_N); Current Source Address Register (Crsa_N) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.4.3

Next Transaction Byte Register n (N0TB_n, N1TB_n)

This register sets the total transfer byte count (DMA transaction) of DMA channel (n = 0 to 15) which is to be executed
next.
N0TB_n is for the Next0 Register Set, and N1TB_n is for the Next1 Register Set.
In register mode, set this register set by using software. In link mode, the descriptor read data is automatically set in the
Next0 Register Set.
These register set values are loaded to the Current Register Set and used for DMA transfer.
Bit: 31
Initial value: 0
R/W: R/W
Bit: 15
0
Initial value:
R/W: R/W
Initial
Bit Bit Name Value
31 to 0 TB All 0
9.4.4

Current Source Address Register (CRSA_n)

This register indicates the DMA transfer source address of DMA channel n (n = 0 to 15).
The values are loaded from the Next0/1 Register Set in register mode or from the descriptor read data in link mode. You
cannot write to this register set using software.
Bit: 31
Initial value:
0
R/W:
R
Bit:
15
0
Initial value:
R/W:
R
Initial
Bit Bit Name Value
31 to 0 CRSA All 0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
0 0 0 0 0
R/W R/W R/W R/W R/W
14 13 12 11 10
0 0 0 0 0
R/W R/W R/W R/W R/W
R/W Description
R/W Transaction Byte
Sets the total transfer byte count.
Caution: Do not start a DMA transaction with 0 set in this register.
30 29 28 27 26
0 0 0 0 0
R R R R R
14 13 12 11 10
0 0 0 0 0
R R R R R
R/W Description
R Current Source Address Register
Indicates the read address of the next DMA transaction.
The value automatically increments during the DMA transaction.
(The value is fixed when 1 is set in SAD of the CHCFG_n register.)
The value increments when a read transfer starts.
Read this register after DMA stops (0 is set in EN of the CHSTAT_n register). (Any value
obtained during the DMA operation should be handled as a reference value.)
25 24 23 22 21
TB
0 0 0 0 0
R/W R/W R/W R/W R/W
9 8 7 6 5
TB
0 0 0 0 0
R/W R/W R/W R/W R/W
25 24 23 22 21
CRSA
0 0 0 0 0
R R R R R
9 8 7 6 5
CRSA
0 0 0 0 0
R R R R R
9. Direct Memory Access Controller
20 19 18 17 16
0 0 0 0 0
R/W R/W R/W R/W R/W
4 3 2 1 0
0 0 0 0 0
R/W R/W R/W R/W R/W
20 19 18 17 16
0 0 0 0 0
R R R R R
4 3 2 1 0
0 0 0 0 0
R R R R R
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