Channel Configuration Register N (Chcfg_N) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.4.9

Channel Configuration Register n (CHCFG_n)

This register controls the DMA transfer operation on DMA channel n (n = 0 to 15).
Bit: 31
DMS
Initial value: 0
R/W: R/W
Bit:
15
0
Initial value:
R/W:
R/W
Initial
Bit Bit Name Value
31 DMS 0
30 REN 0
29 RSW 0
28 RSEL 0
27 SBE 0
26, 25 — 0
24 DEM 0
23 — 0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
REN RSW RSEL SBE -
0 0 0 0 0
R/W R/W R/W R/W R
14 13 12 11 10
SDS[3:0] -
0 0 0 0 0
R/W R/W R/W R R/W
R/W Description
R/W DMA Mode Select
Sets the DMA mode.
0: Register mode (initial value)
1: Link mode
R/W Register Set Enable
After a DMA transaction is completed, DMA transfers are continued using the Next Register
Set selected by RSEL. This bit is valid only in register mode.
0: Does not continue DMA transfers.
1: Continues DMA transfers.
Set condition(s):
• When 1 is written to this bit
Clear condition(s):
• When 0 is written to this bit
• When a DMA transaction is completed, with REN set to 1
R/W Register Select Switch
Inverts RSEL automatically after a DMA transaction is completed. This bit is valid only in
register mode.
0: Does not invert RSEL automatically after a DMA transaction (initial value).
1: Inverts RSEL automatically after a DMA transaction.
R/W Register Set Select
Selects the Next Register Set to be executed next. This bit is valid only in register mode.
When RSW is set to 1, this bit is inverted automatically when a DMA transaction is
completed.
0: Executes the Next0 Register Set (initial value).
1: Executes the Next1 Register Set.
Transition condition(s):
• When a DMA transaction is completed, with RSW set to 1
R/W Sweep Buffer Enable
Selects whether to sweep (write) the data already read into the buffer and stop the DMA
transfer if the Enable bit is cleared to 0 during a DMA transaction.
The sweep mode is available only when REQD is set to 0.
0: Stops the DMA transfer without sweeping the buffer (initial value).
1: Stops the DMA transfer after sweeping the buffer.
R Reserved area. Set 0. A read operation results in 0 being read.
R/W DMA Transfer End Interrupt Mask
Masks the DMA transfer end interrupt for register mode transfer.
If 1 is set in this bit when a DMA transfer end interrupt is output, the DMA transfer end
interrupt signal is not asserted. In this case, DEM is cleared to 0 automatically.
0: Does not mask the DMA transfer end interrupt (initial value).
1: Masks the DMA transfer end interrupt.
Clear condition(s):
• When a DMA transaction is completed with DEM set to 1
R Reserved area. Set 0. A read operation results in 0 being read.
25 24 23 22 21
- DEM - TM DAD
0 0 0 0 0
R R/W R R/W R/W
9 8 7 6 5
AM[2:0] - LVL HIEN
0 0 0 0 0
R/W R/W R R/W R/W
9. Direct Memory Access Controller
20 19 18 17 16
SAD DDS[3:0]
0 0 0 0 0
R/W R/W R/W R/W R/W
4 3 2 1 0
LOEN REQD SEL[2:0]
0 0 0 0 0
R/W R/W R/W R/W R/W
9-20