Noise Cancellation Function - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
15.7

Noise Cancellation Function

Figure 15.37 shows the configuration of the noise filter used for noise cancellation. The noise filter consists of two
stages of flip-flop circuits and a match-detection circuit. When the level on the pin matches in three consecutive samples
taken at the set sampling interval, the matching level continues to be conveyed internally until the level on the pin again
matches in three consecutive samples.
In asynchronous mode, the noise cancellation function can be applied on the RXDn input signal. The period of the base
clock (1/16th of a bit-period when SEMR.ABCS = 0 and 1/8th of a bit-period when SEMR.ABCS = 1) is the sampling
interval.
If the base clock is stopped with the noise filter enabled and then the clock input is started again, the noise filter operation
resumes from where the clock was stopped. If SCR.TE and SCR.RE are set to 0 during base clock input, all of the noise
filter flip-flop values are initialized to 1. Accordingly, if the input data is 1 when reception operation resumes, it is
determined that a level match is detected and is conveyed to the internal signal. When the level being input corresponds
to 0, the initial output of the noise filter is retained until the level matches in three consecutive samples.
RXDn
input signal
Base clock for
asynchronous mode
Figure 15.37 Block Diagram of Digital Noise Filter Circuit
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
D Q D Q
CLK CLK
15. Serial Communications Interface
Not match
Match
D Q
CLK
Com-
parator
RXDn
internal signal
Bit NFEN
15-58