Spbssl Pin Control; Flags - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.5.12

SPBSSL Pin Control

Negation conditions of the SPBSSL pin are as follows.
(1) External Address Space Read Mode
(a) Normal read operation (RBE bit in DRCR = 0)
SPBSSL negated after completing the data transfer and t2 cycle.
(b) Burst read without automatic SPBSSL negation (RBE bit in DRCR = 1, SSLE bit in DRCR = 0)
SPBSSL negated after completing the data transfer and t2 cycle.
(c) Burst read with automatic SPBSSL negation (RBE bit in DRCR = 1, SSLE bit in DRCR = 1)
• SPBSSL negated after t2 cycle when the read address is not continuous with the previously read address
• SPBSSL negated after the SSLN bit in DRCR is set to 1
(2) SPI Operating Mode
(a) SPBSSL pin assertion not retained (SSLKP bit in SMCR = 0)
SPBSSL negated after completing the data transfer and t2 cycle.
(b) SPBSSL pin assertion retained (SSLKP bit in SMCR = 1)
SPBSSL not negated.
When to be negated, data should be transferred after setting the SSLKP bit to 0.
17.5.13

Flags

This module has two flag bits SSLF and TEND in CMNSR. These bits are read-only bits.
(1) SSLF Bit
This bit indicates the SPBSSL pin status. The status is 1 when the SPBSSL is asserted, and the status is 0 when the
SPBSSL is negated.
(2) TEND Bit
This bit indicates whether transfer of data is in progress or the transfer of data has ended.
During t1 time period, data transfer, t2 time period, t3 time period, and waiting for read access by burst read and SPBSSL
automatic negation, the TEND bit is read as 0 to indicate that the transfer of data is in progress.
When other than the above, the TEND bit is read as 1 to indicate that transfer of data has ended.
(3) Register Re-writing Timing
The status of the TEND bit determines the rewritable registers.
The registers which can be written to, except the SSLN bit in DRCR, should be modified when TEND = 1. Read
SMRDR0 and SMRDR1 when TEND = 1. CMNSR can always be read.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
17. SPI Multi I/O Bus Controller
17-52