Changing The Frequency; Changing The Division Ratio - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
6.5

Changing the Frequency

The frequency of the CPU clock (Iφ) can be changed by changing the division rate of divider. The division rate can be
changed by software through the frequency control register (FRQCR).
6.5.1

Changing the Division Ratio

The division rate of divider can be changed by the following operation.
1. In the initial state, IFC[1:0] = B'11.
2. Set the desired value in the IFC[1:0] bits. Note that if the wrong value is set, this LSI will malfunction.
3. After the register bits (IFC[1:0]) have been set, the clock is supplied of the new division ratio.
Note: When executing the WFI instruction after changing the frequency, be sure to read the frequency control register
(FRQCR) to confirm that the new setting is in place and read the ISBUSY0 bit in the CPU status register
(CPUSTS) to confirm that it is set to 0 beforehand.
For the CPUSTS register, see section 42, Power-Down Modes.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
6. Clock Pulse Generator
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