Rscan0Gctr - Global Control Register - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.6 RSCAN0GCTR — Global Control Register
Access: Can be read/written in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 0088
Initial value: 0000 0005
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 21.20
Bit Position
31 to 17
16
15 to 11
10
9
8
7 to 3
2
1, 0
TSRST Bit
This bit is used to reset the timestamp counter. When this bit is set to 1, the RSCAN0GTSC register is
cleared to 0000
THLEIE Bit
When the THLEIE bit is set to 1 and the THLES flag in the RSCAN0GERFL register is set to 1, an
interrupt request is generated. Modify this bit only in global reset mode.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
H
28 27 26
— — —
0 0 0
R R R
12 11 10
— — THLEIE MEIE
0 0 0
R R R/W R/W
RSCAN0GCTR register contents
Bit Name Function
Reserved These bits are always read as 0. The write value should always be 0.
TSRST Timestamp Counter Reset
Setting the TSRST bit to 1 resets the timestamp counter. This bit is always read
as 0.
Reserved These bits are always read as 0. The write value should always be 0.
THLEIE Transmit History Buffer Overflow Interrupt Enable
0: Transmit history buffer overflow interrupt is disabled.
1: Transmit history buffer overflow interrupt is enabled.
MEIE FIFO Message Lost Interrupt Enable
0: FIFO message lost interrupt is disabled.
1: FIFO message lost interrupt is enabled.
DEIE DLC Error Interrupt Enable
0: DLC error interrupt is disabled.
1: DLC error interrupt is enabled.
Reserved These bits are always read as 0. The write value should always be 0.
GSLPR Global Stop Mode
0: Other than global stop mode
1: Global stop mode
GMDC[1:0] Global Mode Select
b1 b0
0
0
1
1
.
H
25 24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
DEIE — —
0 0 0 0
R/W R R
0: Global operating mode
1: Global reset mode
0: Global test mode
1: Setting prohibited
21. CAN Interface
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
— — — GSLPR
0 0 0 1
R R R R/W
17 16
— TSRST
0 0
R R/W
1 0
GMDC[1:0]
0 1
R/W R/W
21-35