South Main Bus; Configuration; Features - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
5.3

South Main Bus

5.3.1

Configuration

On-chip RAM and external ROM and RAM are connected to the south main bus. Figure 5.3 shows the configuration of
the south main bus.
Video display
controller 5
IV1-, 3-, 5-BUS
Cortex-A9
AXI128IC2 bus
SLV0
L2 cache memory
(L2C-310)
Bus state SPI multi I/O
bus controller
controller
Figure 5.3 South Main Bus Configuration
5.3.2

Features

Table 5.3 shows the features of the south main bus.
Table 5.3 South Main Bus
Item
Bus protocol
Bus system configuration
Bus clock frequency
Bus width
Arbitration
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Video display
controller 5
IV6-BUS
AXI128IC3 bus
SLV1 SLV2
On-chip
data
retention
RAM
South main bus
SLV3 SLV4 SLV5
On-chip On-chip On-chip
large-capacity large-capacity large-capacity large-capacity
RAM RAM RAM
page 0 page 1 page 2
Description
AMBA AXI protocol
AXI interconnect with multi-layer configuration for all channels
Bφ
128 bits
Round robin
5. LSI Internal Bus
North main bus
Ethernet Bus
* 1
AVB bridge 1
SLV6 SLV7
On-chip On-chip
large-capacity
RAM* 2
RAM
page 3 page 4
Note 1. RZ/A1LU only
Note 2. RZ/A1L and RZ/A1LU only
Bus
bridge 2
5-5