Riicnmr3 - I²C Bus Mode Register 3 - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.3.5 RIICnMR3 — I²C Bus Mode Register 3
Access: RIICnMR3 is a 32-bit readable/writable register.
RIICnMR3L and RIICnMR3H are 16-bit readable/writable registers.
RIICnMR3LL, RIICnMR3LH, RIICnMR3HL, and RIICnMR3HH are 8-bit readable/writable registers.
Address: RIICnMR3: <RIICn_base> + 0010
RIICnMR3L: <RIICn_base> + 0010
RIICnMR3LL: <RIICn_base> + 0010
RIICnMR3HH: <RIICn_base> + 0013
Initial Value: 0000 0000
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 18.10
Bit Position
31 to 8
7
6
5
4
3
2
1, 0
Note 1.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
, RIICnMR3H: <RIICn_base> + 0012
H
, RIICnMR3LH: <RIICn_base> + 0011
H
H
This register is initialized by any reset.
H
28 27 26
— — —
0 0 0
R R R
12 11 10
— — —
0 0 0
R R R
RIICnMR3 register contents
Bit Name Function
— Reserved
These bits are read as 0. The write value should be 0.
SMBE SMBus/I
0: I
1: SMBus selection
*2
WAIT WAIT
0: No WAIT
1: WAIT
*2
RDRFS RDRF Flag Set Timing Selection
0: The RDRF flag is set at the rising edge of the ninth SCL clock cycle.
1: The RDRF flag is set at the rising edge of the eighth SCL clock cycle.
*1
ACKWP ACKBT Write Protect
0: Modification of the ACKBT bit is disabled.
1: Modification of the ACKBT bit is enabled.
*1
ACKBT Transmit Acknowledge
0: A 0 is sent as the acknowledge bit (ACK transmission).
1: A 1 is sent as the acknowledge bit (NACK transmission).
ACKBR Receive Acknowledge
0: A 0 is received as the acknowledge bit (ACK reception).
1: A 1 is received as the acknowledge bit (NACK reception).
NF[1:0] Noise Filter Stage Selection
b1 b0
0 0: Noise of up to one IIC φ cycle is filtered out (single-stage filter).
0 1: Noise of up to two IIC φ cycles is filtered out (2-stage filter).
1 0: Noise of up to three IIC φ cycles is filtered out (3-stage filter).
1 1: Noise of up to four IIC φ cycles is filtered out (4-stage filter).
If it is attempted to write 1 to both ACKWP and ACKBT bits, the ACKBT bit cannot be set to 1.
H
, RIICnMR3HL: <RIICn_base> + 0012
H
25 24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
— — SMBE WAIT
0 0 0 0
R R R/W R/W
2
C Bus Selection
2
C bus selection
(The period between ninth clock cycle and first clock cycle is not held low.)
(The period between ninth clock cycle and first clock cycle is held low.)
Low-hold is released by reading RIICnDRR.
(The SCL line is not held low at the falling edge of the eighth clock cycle.)
(The SCL line is held low at the falling edge of the eighth clock cycle.) Low-
hold is released by writing a value to the ACKBT bit.
18. I²C Bus Interface
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
RDRFS ACKWP ACKBT ACKBR
0 0 0 0
R/W W R/W R
,
H
17 16
— —
0 0
R R
1 0
NF[1:0]
0 0
R/W R/W
18-18