Axi Bus Response Error Clear Register 0 (Axirerrclr0) - Renesas RZ/A Series User Manual

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RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group

AXI Bus Response Error Clear Register 0 (AXIRERRCLR0)

This register clears the AXI bus response error status.

Initial value:

Initial value:

Note: * This bit is only present in the RZ/A1LU. For the RZ/A1L and RZ/A1LC, the write value should always be 0.

R01UH0437EJ0600 Rev.6.00

Jan 29, 2021

This bit is always read as 0. The write value should always be 0.

JCURRESP[1:0] Clear

Writing 1 to this bit clears the JCURRESP[1:0] bits to 00.

This bit is always read as 0.

This bit is always read as 0. The write value should always be 0.

JCUBRESP[1:0] Clear

Writing 1 to this bit clears the JCUBRESP[1:0] bits to 00.

This bit is always read as 0.

This bit is always read as 0. The write value should always be 0.

ETHRRESP[1:0] Clear

Writing 1 to this bit clears the ETHRRESP[1:0] bits to 00.

This bit is always read as 0.

This bit is always read as 0. The write value should always be 0.

ETHBRESP[1:0] Clear

Writing 1 to this bit clears the ETHBRESP[1:0] bits to 00.

This bit is always read as 0.

These bits are always read as 0. The write value should always be 0.

CEUBRESP[1:0] Clear

Writing 1 to this bit clears the CEUBRESP[1:0] bits to 00.

This bit is always read as 0.

These bits are always read as 0. The write value should always be 0.

5. LSI Internal Bus

Rz/a1 series Rz/a1lu series Rz/a1lc series