Burst Rom (Clocked Synchronous) Interface - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
8.5.9

Burst ROM (Clocked Synchronous) Interface

The burst ROM (clocked synchronous) interface is supported to access a ROM with a synchronous burst function at high
speed. The burst ROM interface accesses the burst ROM in the same way as a normal space. This interface is valid only
for area 0.
In the first access cycle, wait cycles are inserted. In this case, the number of wait cycles to be inserted is specified by the
W3 to W0 bits in CS0WCR. In the second and subsequent cycles, the number of wait cycles to be inserted is specified by
the BW1 and BW0 bits in CS0WCR.
While the burst ROM (clocked synchronous) is accessed, the BS signal is asserted only for the first access cycle and an
external wait input is also valid for the first access cycle.
When the bus width is 16 bits, the burst length must be specified as 8. When the bus width is 32 bits, the burst length
must be specified as 4. The burst ROM interface does not support the 8-bit bus width for the burst ROM.
The burst ROM interface performs burst operations for all read access. For example, in a 32-bit access over a 16-bit bus,
valid 16-bit data is read two times and invalid 16-bit data is read six times. These invalid data read cycles increase the
memory access time and degrade the program execution speed and DMA transfer speed. To prevent this problem, it is
recommended using a read in a 16-byte or more access size. The burst ROM interface performs write access in the same
way as normal space access.
T1
CKIO
A25 to A0
CS0
RD/WR
RD
D15 to D0
WAIT
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 8.39 Burst ROM Access Timing (Clocked Synchronous) (Burst Length = 8, Wait Cycles Inserted in
First Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Tw Tw T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb
8. Bus State Controller
T2B Twb T2B Twb T2
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