Spi Mode Command Setting Register (Smcmr); Spi Mode Address Setting Register (Smadr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.4.10

SPI Mode Command Setting Register (SMCMR)

SMCMR is a 32-bit register that sets the commands issued in SPI operating mode.
The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be
guaranteed.
Bit:
31
-
Initial value: 0
R/W:
R
Bit:
15
-
Initial value:
0
R/W:
R
Bit Bit Name
31 to 24 ―
23 to 16 CMD[7:0]
15 to 8 ―
7 to 0 OCMD[7:0]
17.4.11

SPI Mode Address Setting Register (SMADR)

SMADR is a 32-bit register that sets the addresses in SPI operating mode.
The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be
guaranteed.
Bit:
31
Initial value: 0
R/W:
R/W
Bit: 15
Initial value: 0
R/W:
R/W
Bit Bit Name
31 to 24 ADR[31:24]
23 to 0 ADR[23:0]
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W
All 0 R
H'00 R/W
All 0 R
H'00 R/W
30 29 28 27 26
ADR[31:24]
0 0 0 0 0
R/W R/W R/W R/W R/W
14 13 12 11 10
0 0 0 0 0
R/W R/W R/W R/W R/W
Initial
Value R/W
H'00 R/W
H'000000 R/W
25 24 23 22 21
- -
0 0 0 0 0
R R R/W R/W R/W
9 8 7 6 5
- -
0 0 0 0 0
R R R/W R/W R/W
Description
Reserved
These bits are always read as 0. The write value should always be 0.
Command
Sets the command.
Reserved
These bits are always read as 0. The write value should always be 0.
Optional Command
Sets the optional command.
25 24 23 22 21
0 0 0 0 0
R/W R/W R/W R/W R/W
9 8 7 6 5
ADR[15:0]
0 0 0 0 0
R/W R/W R/W R/W R/W
Description
Address
Sets the value of bits 31 to 24 when the serial flash address is output in
32-bit units.
This setting is valid when ADE[3] in SMENR is 1.
Address
Sets the address.
17. SPI Multi I/O Bus Controller
20 19 18 17 16
CMD[7:0]
0 0 0 0 0
R/W R/W R/W R/W R/W
4 3 2 1 0
OCMD[7:0]
0 0 0 0 0
R/W R/W R/W R/W R/W
20 19 18 17 16
ADR[23:16]
0 0 0 0 0
R/W R/W R/W R/W R/W
4 3 2 1 0
0 0 0 0 0
R/W R/W R/W R/W R/W
17-18