Note; Divided Output Of Dack0 And Tend0 - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.9

Note

9.9.1

Divided Output of DACK0 and TEND0

When transferring 4 bytes or more to an 8-bit or 16-bit external device or transferring 2 bytes or more to an 8-bit external
device, each DMA transfer unit is divided into multiple bus cycles. Note that, if the setting is such that DMA transfer is
divided into multiple bus cycles and CS is negated between bus cycles, the DACK0 output and the TEND0 output is
divided to align data as with CS. Figure 9.38 shows an example.
CKIO
Address
CS
RD
Data
WE
DACK0
(Active low)
TEND0
(Active low)
WAIT
Figure 9.38 Example of TEND0 Divided Output Timing
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
T1 T2 Taw
9. Direct Memory Access Controller
T1 T2
9-76