Dma Status End Register (Dstat_End_0_7); Dma Status End Register (Dstat_End_8_15) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.4.19

DMA Status END Register (DSTAT_END_0_7)

This register indicates the END bit status of the CHSTAT_n register (n = 0 to 7).
Even if you write to this register, the values of the individual bits do not change.
Bit: 31
-
Initial value: 0
R/W: R
Bit: 15
-
0
Initial value:
R/W: R
Initial
Bit Bit Name Value
31 to 8 — All 0
7 END7 0
6 END6 0
5 END5 0
4 END4 0
3 END3 0
2 END2 0
1 END1 0
0 END0 0
9.4.20

DMA Status END Register (DSTAT_END_8_15)

This register indicates the END bit status of the CHSTAT_n register (n = 8 to 15).
Even if you write to this register, the values of the individual bits do not change.
Bit: 31
-
Initial value:
0
R/W:
R
Bit: 15
-
0
Initial value:
R/W:
R
Initial
Bit Bit Name Value
31 to 8 — All 0
7 END15 0
6 END14 0
5 END13 0
4 END12 0
3 END11 0
2 END10 0
1 END9 0
0 END8 0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
R/W Description
R Reserved area. Set 0. A read operation results in 0 being read.
R Indicates the END bit status of DMA channel 7.
R Indicates the END bit status of DMA channel 6.
R Indicates the END bit status of DMA channel 5.
R Indicates the END bit status of DMA channel 4.
R Indicates the END bit status of DMA channel 3.
R Indicates the END bit status of DMA channel 2.
R Indicates the END bit status of DMA channel 1.
R Indicates the END bit status of DMA channel 0.
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
R/W Description
R Reserved area. Set 0. A read operation results in 0 being read.
R Indicates the END bit status of DMA channel 15.
R Indicates the END bit status of DMA channel 14.
R Indicates the END bit status of DMA channel 13.
R Indicates the END bit status of DMA channel 12.
R Indicates the END bit status of DMA channel 11.
R Indicates the END bit status of DMA channel 10.
R Indicates the END bit status of DMA channel 9.
R Indicates the END bit status of DMA channel 8.
25 24 23 22 21
- - - - -
0 0 0 0 0
R R R R R
9 8 7 6 5
- - END7 END6 END5
0 0 0 0 0
R R R R R
25 24 23 22 21
- - - - -
0 0 0 0 0
R R R R R
9 8 7 6 5
- - END15 END14 END13 END12 END11 END10 END9
0 0 0 0 0
R R R R R
9. Direct Memory Access Controller
20 19 18 17 16
- - - - -
0 0 0 0 0
R R R R R
4 3 2 1 0
END4 END3 END2 END1 END0
0 0 0 0 0
R R R R R
20 19 18 17 16
- - - - -
0 0 0 0 0
R R R R R
4 3 2 1 0
END8
0 0 0 0 0
R R R R R
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