Interrupt Operations; Interrupt Request Signals - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
22.4

Interrupt Operations

22.4.1

Interrupt request signals

Table 22-38 Causes of interrupts in the single mode
Symbol IEBBTD
IEBBnIEBE
IEBBnSTRF
IEBBnSTSF
IEBBnETRF
IEBBnEFMF
IEBBnFOVE
WRREQ Occurs
RDREQ Occurs
a)
If the frame data ends with a NACK signal, IEBBTV and IEBBTSTA are triggered by setting the frame
completion indicating bit IEBBnISR.IEBBnEFMF (to 1).
At this time, the IEBBTERR and IEBBTV interrupts are triggered by a NACK reception error.
Three interrupts (IEBBTV, IEBBTSTA, and IEBBTERR) occur at the same time.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Various interrupts occur in response to the eight interrupt requests below. The high
level width of each interrupt signal is one P0φ clock cycle.
The interrupts that occur differ depending on whether the system is in the single or
FIFO mode.
(1) Single mode
The causes of interrupts in the single mode are shown blow.
IEBBTV IEBBTERR IEBBTSTA
Occurs Occurs
Occurs
Occurs
Occurs
Occurs
Interrupt cause
Communication error
(When the IEBBnISR.IEBBnIEBE bit = 1)
Note that IEBBnIEBE occurs when the
following bits of the IEBBnESR register =
1.
• Timing error (IEBBnTIME)
• Parity error (IEBBnPARE)
• NACK reception error (IEBBnNACE)
• Underrun error (IEBBnUNRE)
• Overrun error (IEBBnOVRE)
Occurs Start request (when the
IEBBnISR.IEBBnSTRF bit = 1)
Occurs Status transmission request
(when the IEBBnISR.IEBBnSTSF bit = 1)
Occurs End of communication
(When the IEBBnISR.IEBBnETRF bit = 1)
Occurs End of frame
(When the IEBBnISR.IEBBnEFMF bit =
a
1)
Frame over
(When the IEBBnISR.IEBBnFOVE bit = 1)
Transmission data write request (when
the IEBBnSSR.IEBBnSTXF bit = 0)
Reception data read request (when the
IEBBnSSR.IEBBnSRXF bit = 1)
22. IEBus Controller
a
b
c
22-72