Timer General Register (Tgr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.3.12

Timer General Register (TGR)

The TGR registers are 16-bit readable/writable registers. This module has eighteen TGR registers, six for channel 0, two
each for channels 1 and 2, four each for channels 3 and 4.
TGRA, TGRB, TGRC, and TGRD function as either output compare or input capture registers. TGRC and TGRD for
channels 0, 3, and 4 can also be designated for operation as buffer registers. TGR buffer register combinations are TGRA
and TGRC, and TGRB and TGRD.
TGRE_0 and TGRF_0 function as compare registers. When the TCNT_0 count matches the TGRE_0 value, an A/D
converter start request can be issued. TGRF can also be designated for operation as a buffer register. TGR buffer register
combination is TGRE and TGRF.
Bit: 15
Initial value: 1
R/W: R/W
Note: The TGR registers must not be accessed in eight bits; they should always be accessed in 16 bits.
TGR registers are initialized to H'FFFF.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
14 13 12 11 10
1 1 1 1 1
R/W R/W R/W R/W R/W
9 8 7 6 5
1 1 1 1 1
R/W R/W R/W R/W R/W
10. Multi-Function Timer Pulse Unit 2
4 3 2 1 0
1 1 1 1 1
R/W R/W R/W R/W R/W
10-41