Data Format - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.5.10

Data Format

This module can input and output data in the order of command, optional command, address, option data, dummy cycle,
and data.
(1) Data Registers
Table 17.5 shows the input and output data.
Table 17.5 Data Registers
Data
Command (8 bits)
Optional command (8 bits)
Address BSZ[1:0] = 00 (one
(32/24 bits) flash memory
connected)
BSZ[1:0] = 01 (two
flash memories
connected)
Option data (8 bits × 4)
Dummy cycle (1 to 8 cycles)
Transfer data
(2) Data Enable
In external address space read mode, transfer enable or disable of the command, optional command, address, option data,
and dummy cycle can be controlled with the CDE, OCDE, ADE[3:0], OPDE[3:0], and DME bits in DRENR,
respectively. The size and number of dummy cycles can be controlled with the data read dummy cycle setting register
(DRDMCR).
When the SPBCLK frequency division ratio is two or larger, either SDR or DDR transfer can be selected for the address,
option data, and read data, using the ADDRE, OPDRE, and DRDRE bits in the data read DDR enable register
(DRDRENR) (RZ/A1LU only).
Similarly, in SPI operating mode, enable or disable of the command, optional command, address, option data, dummy
cycle, and transfer data can be controlled with the CDE, OCDE, ADE[3:0], OPDE[3:0], DME, and SPIDE[3:0] bits in
SMENR, respectively. However, disabling all the above parameters is prohibited in SPI operating mode. At least one of
them except dummy cycle must be enabled. The size and number of dummy cycles can be controlled with the SPI mode
dummy cycle setting register (SMDMCR).
When the SPBCLK frequency division ratio is two or larger, either SDR or DDR transfer can be selected for the address,
option data, and transfer data, using the ADDRE, OPDRE, and SPIDRE bits in the SPI mode DDR enable register
(SMDRENR) (RZ/A1LU only).
For the address and option data in external address space read mode; and the address, option data, and transfer data in SPI
operating mode, the enable bit setting allowed is determined according to the transfer data size. For the allowed setting
combinations of the enable bits and transfer data size, refer to the description of the pertinent register.
If data is disabled, that data is skipped, and input and output of the next data is carried out. The command, optional
command, address, and option data are always output. During dummy cycles, the state of the used pins is Hi-Z. In
external address space read mode, data is always input; and in SPI operating mode, input and output of data is determined
based on the settings of the SPIRE and SPIWE bits in SMCR.
There are some restrictions on dummy cycle insertion; refer to the description of the DME bits in DRENR and SMENR
for details.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
External Address Space Read Operation SPI Operation
CMD[7:0] bits in DRCMR
OCMD[7:0] bits in DRCMR
32 bits: DREAR.EAV[6:1 to 0] bits + lower
[25 to 24:0] bits of the read address.
24 bits: Lower [23:0] bits of the read
address
32 bits: DREAR.EAV[7:1 to 0] bits + lower
[25 to 24:1] bits of the read address.
24 bits: Lower [24:1] bits of the read
address
DROPR
DRDMCR
Normal read: 8, 16, and 32 bits
Burst read: 64 × RBURST bits
17. SPI Multi I/O Bus Controller
CMD[7:0] bits in SMCMR
OCMD[7:0] bits in SMCMR
32 bits: ADR[31:0] bits in SMADR
24 bits: ADR[23:0] bits in SMADR
SMOPR
SMDMCR (only when read)
Read: SMRDR0, SMRDR1
Write: SMWDR0, SMWDR1
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