Pin Control; System Configuration Example - Renesas RZ/A Series User Manual

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RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group

Pin Control

According to the MSTR bit in the control register (SPCR), this module can automatically switch pin directions and

output modes. Table 16.5 shows the relationship between pin states and bit settings.

Relationship between Pin States and Bit Settings

(SPI operation)

(SPI operation)

Note 1. When SSL is at the non-active level or the SPE bit in SPCR is cleared to 0, the pin state is

This module in master mode (SPI operation) determines MOSI signal values during the SSL negation period (including

the SSL retention period during a burst transfer) according to MOIFE and MOIFV bit settings in SPPCR, as shown in

MOSI Signal Value Determination during SSL Negation Period

(1) Master/Slave (with This LSI Acting as Master)

Figure 16.2 shows a master/slave system configuration example when this LSI is used as a master. In master/slave

configuration, the SSL output of this LSI (master) is not used. The SSL input of the slave is fixed to the low level, and the

slave is always maintained in a selected state. In the transfer format corresponding to the case where the CPHA bit in the

control register (SPCR) is 0, there are slave devices for which the SSL signal cannot be fixed to the active level. In

situations where the SSL signal cannot be fixed, the SSL output of this LSI should be connected to the SSL input of the

slave device.

This LSI (master) always drives the RSPCK and MOSI. The slave always drives the MISO.

Master/Slave Configuration Example (This LSI = Master)

R01UH0437EJ0600 Rev.6.00

Jan 29, 2021

MOSI Signal Value during SSL Negation Period

Last output value from previous transfer (The value is undefined when CPHA is 0)

This LSI (master)

16. Renesas Serial Peripheral Interface

CMOS output/Hi-Z

Rz/a1 series Rz/a1lu series Rz/a1lc series