RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
11.2.2
Details of OSTM Registers
11.2.2.1
OSTMnCMP
Depending on the mode of operation, this register holds the start value for the down-counter or the
value for comparison with that of the counter.
Initial value:
Bit
31
30
29
R/W
R/W
R/W
R/W
Bit
15
14
13
R/W
R/W
R/W
R/W
Table 11.4
Bit Position
31 to 0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
—
OSTM Compare Register
Access:
This register is readable/writable in 32-bit units.
Address:
<OSTMn_base>
0000 0000
H
28
27
26
R/W
R/W
R/W
12
11
10
R/W
R/W
R/W
OSTMnCMP register contents
Bit Name
Function
OSTMnCMP
• In interval timer mode: start value of the down-counter
[31:0]
• In free-running comparison mode: value for comparison
25
24
23
22
OSTMnCMP[31:16]
R/W
R/W
R/W
R/W
9
8
7
6
OSTMnCMP[15:0]
R/W
R/W
R/W
R/W
21
20
19
18
R/W
R/W
R/W
R/W
5
4
3
2
R/W
R/W
R/W
R/W
11. OS Timer
17
16
R/W
R/W
1
0
R/W
R/W
11-3