Transfer Format - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.5.9

Transfer Format

(1) SPBSSL Pin Enable Polarity Control
The enable polarity of the SPBSSL pin can be changed with the SSLP bit in CMNCR.
(2) SPBCLK Output
The SPBCLK output direction during SPBSSL negation can be set with the CPOL bit in CMNCR.
(3) Data Transmission and Reception Timing
Data transmission and reception timing is different between SDR transfer and DDR transfer (RZ/A1LU only).
During SDR transfer, data is transmitted and received at either the odd or even edges. The data transmission timing can
be set to the odd or even edge with the CPHAT bit in CMNCR. Similarly, the data reception timing can be set to the odd
or even edge with the CPHAR bit in CMNCR.
During DDR transfer (RZ/A1LU only), data is transmitted and received at both the odd and even edges. The first data
transmission timing can be set to the odd or even edge with the CPHAT bit in CMNCR. Similarly, the first data reception
timing can be set to the odd or even edge with the CPHAR bit in CMNCR.
(4) Delay Settings
t1 is the time period from SPBSSL pin assertion to SPBCLK oscillation (clock delay). It can be set with the SCKDL[2:0]
bits in SSLDR. t2 is the time period till the SPBSSL signal negation after the SPBCLK oscillation is stopped (SPBSSL
negation delay). It can be set with the SLNDL[2:0] bits in SSLDR. t3 is the time period required to prevent SPBSSL
signal assertion for the next transfer after the end of the previous transfer (next access delay). It can be set with the
SPNDL[2:0] bits in SSLDR.
SPBCLK
(CPOL = 0)
SPBCLK
(CPOL = 1)
Output pin
(CPHAT = 0)
Output pin
(CPHAT = 1)
Sampling
(CPHAR = 0)
Sampling
(CPHAR = 1)
SPBSSL
(SSLP = 0)
SPBSSL
(SSLP = 1)
Figure 17.18 SDR Transfer Format
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
t1
17. SPI Multi I/O Bus Controller
t2 t3
17-43