Functional Block Diagram - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
23.3

Functional Block Diagram

Figure 23.2 Functional Block Diagram
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Transmitter Parity
data generator
handling
Transmitter Frame
control counter
Receiver
control
Receiver Parity
data check
handling
BMC and
preamble
encoding
Oversampling clock
Clock
recovery and
frame counter
BMC decode
and preamble
detection
23. Renesas SPDIF Interface
SPDIF_OUT
AUDIO_X1
AUDIO_X2
AUDIO_CLK
SPDIF_IN
23-2