Bus State Controller; Features - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
8.

Bus State Controller

The bus state controller outputs control signals for various types of memory and external devices that are connected to
the external address space. The functions of this module enable this LSI to connect directly with SRAM, SDRAM, and
other memory storage devices, and external devices.
8.1

Features

1. External address space
A maximum of 64 Mbytes for each of areas CS0 to CS5.
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Can specify the normal space interface, SRAM interface with byte selection, burst ROM (clocked synchronous or
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asynchronous), MPX-I/O, and SDRAM memory type for each address space.
Can select the data bus width (8, 16, or 32 bits) for each of address spaces.
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Controls insertion of wait cycles for each address space.
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Controls insertion of wait cycles for each read access and write access.
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Can set independent idle cycles during the continuous access for five cases: read-write (in same space/different
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spaces), read-read (in same space/different spaces), the first cycle is a write access.
2. Normal space interface
Supports the interface that can directly connect to the SRAM.
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3. Burst ROM interface (clocked asynchronous)
High-speed access to the ROM that has the page mode function.
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4. MPX-I/O interface
Can directly connect to a peripheral LSI that needs an address/data multiplexing.
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5. SDRAM interface
Can set the SDRAM in up to two areas.
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Multiplex output for row address/column address.
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Efficient access by single read/single write.
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High-speed access in bank-active mode.
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Supports an auto-refresh and self-refresh.
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Supports a power-down mode.
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Issues MRS and EMRS commands.
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6. SRAM interface with byte selection
Can connect directly to a SRAM with byte selection.
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7. Burst ROM interface (clocked synchronous)
Can connect directly to a burst ROM of the clocked synchronous type.
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8. Refresh function
Supports the auto-refresh and self-refresh functions.
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Specifies the refresh interval using the refresh counter and clock selection.
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Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8).
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9. Usage as interval timer for refresh counter
Generates an interrupt request at compare match.
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10. Detection of long wait state for access by the signal on the external WAIT pin.
A timeout detection condition is specifiable per CS space.
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Once timeout is detected, the external WAIT function is disabled and a timeout detection interrupt request is
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issued.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
8. Bus State Controller
8-1