Master Receive Operation - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.5.4

Master Receive Operation

In master receive operation, the RIIC as a master device outputs the SCL (clock) signal, receives data
from the slave device, and returns acknowledgements. Since the RIIC must start by sending a slave
address to the corresponding slave device, this part of the procedure is performed in master transmit
mode, but the subsequent steps are in master receive mode.
Figure 18.10 shows an example of usage for the master reception of 3 or more bytes (7-bit address
format), Figure 18.14 shows an example of usage for the master reception of 1 or 2 bytes (7-bit
address format), and Figure 18.11 to Figure 18.13 show the timing of operations in master reception.
The following describes the procedure and operations for master reception.
(1) Set the RIICnCR1.IICRST bit to 1 (RIIC reset) and then set the RIICnCR1.ICE bit to 1 (internal
reset) with the RIICnCR1.ICE bit cleared to 0 (RIICnSCL and RIICnSDA pins not driven). This
initializes the internal state and the various flags of RIICnSR1. After that, set registers
RIICnSARy, RIICnSER, RIICnMR1, RIICnBRH, and RIICnBRL (y = 0 to 2), and set the other
registers as necessary (for initial settings of the RIIC, see Figure 18.5). When the necessary
register settings have been completed, set the RIICnCR1.IICRST bit to 0 (for release from the
reset state). This step is not necessary if initialization of the RIIC has already been completed.
(2) Read the RIICnCR2.BBSY flag to check that the bus is open, and then set the RIICnCR2.ST bit
to 1 (start condition issuance request). Upon receiving the request, the RIIC issues a start
condition. When the RIIC detects the start condition, the BBSY flag and the RIICnSR2.START
flag are automatically set to 1 and the ST bit is automatically cleared to 0. At this time, if the start
condition is detected and the levels for the SDA output and the levels on the SDA line have
matched while the ST bit is 1, the RIIC recognizes that issuing of the start condition as requested
by the ST bit has been successfully completed, and the RIICnCR2.MST and TRS bits are
automatically set to 1, placing the RIIC in master transmit mode. The RIICnSR2.TDRE flag is
also automatically set to 1 in response to setting of the TRS bit to 1.
(3) Check that the RIICnSR2.TDRE flag is 1, and then write the value for transmission (the first byte
indicates the slave address and value of the R/W# bit) to RIICnDRT. Once the data for
transmission are written to RIICnDRT, the TDRE flag is automatically cleared to 0, the data are
transferred from RIICnDRT to RIICnDRS, and the TDRE flag is again set to 1. Once the byte
containing the slave address and R/W# bit has been transmitted, the value of the RIICnCR2.TRS
bit is automatically updated to select transmit or receive mode in accord with the value of the
transmitted R/W# bit. If the value of the R/W# bit was 1, the RIICnCR2.TRS bit is cleared to 0
on the rising edge of the ninth cycle of SCL (the clock signal), placing the RIIC in master receive
mode. At this time, the TDRE flag is automatically cleared to 0 and the RIICnSR2.RDRF flag is
automatically set to 1.
Since the RIICnSR2.NACKF flag being 1 at this time indicates that no slave device recognized
the address or there was an error in communications, write 1 to the RIICnCR2.SP bit to issue a
stop condition.
For master reception from a device with a 10-bit address, start by using master transmission to
issue the 10-bit address, and then issue a restart condition. After that, transmitting 1111 0
two higher-order bits of the slave address, and the R bit places the RIIC in master receive mode.
(4) Dummy read RIICnDRR after confirming that the RIICnSR2.RDRF flag is 1; this makes the
RIIC start output of the SCL (clock) signal and start data reception.
(5) After 1 byte of data has been received, the RIICnSR2.RDRF flag is set to 1 on the rising edge of
the eighth or ninth cycle of SCL clock (the clock signal) as selected by the RIICnMR3.RDRFS
bit. Reading out RIICnDRR at this time will produce the received data, and the RDRF flag is
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
18. I²C Bus Interface
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