Spi Mode Control Register (Smcr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.4.9

SPI Mode Control Register (SMCR)

SMCR is a 32-bit register that sets the operation in SPI operating mode.
The settings of this register should be changed when the TEND flag in CMNSR is 1; otherwise, the operation cannot be
guaranteed.
Bit:
31
-
Initial value: 0
R/W:
R
Bit:
15
-
Initial value:
0
R/W:
R
Bit Bit Name
31 to 9 ―
8 SSLKP
7 to 3 ―
2 SPIRE
1 SPIWE
0 SPIE
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W
All 0 R
0 R/W
All 0 R
0 R/W
0 R/W
0 W
25 24 23 22 21
- - - - -
0 0 0 0 0
R R R R R
9 8 7 6 5
- SSLKP - - -
0 0 0 0 0
R R/W R R R
Description
Reserved
These bits are always read as 0. The write value should always be 0.
SPBSSL Signal Level
Determines the SPBSSL status after the end of transfer.
0: SPBSSL signal is negated at the end of transfer.
1: SPBSSL signal level is maintained from the end of transfer to the start
of next access.
Reserved
These bits are always read as 0. The write value should always be 0.
Data Read Enable
Enables reading in SPI operating mode.
0: Data reading disabled
1: Data reading enabled
Note: When the transfer data bit size is set to 2 bits or 4 bits with the
SPIDB[1:0] bits, the SPIRE and SPIWE bits should not be set to 1
at the same time.
Data Write Enable
Enables writing in SPI operating mode.
0: Data writing disabled
1: Data writing enabled
Note: When the transfer data bit size is set to 2 bits or 4 bits with the
SPIDB[1:0] bits, the SPIRE and SPIWE bits should not be set to 1
at the same time.
SPI Data Transfer Enable
Data is transferred by setting this bit to 1.
This bit is enabled only when the TEND bit in CMNSR is set to 1. The
operation cannot be guaranteed when this bit is set to 1 with the TEND bit
set to 0.
This bit is always read as 0.
Note: When the SPBSSL pin is de-asserted, the command, optional
command, address, and option data that are output enabled are
output even if the SPIRE and SPIWE bits are set to 0. When the
SPBSSL pin is asserted, follow the notes described in section
17.6.2, Notes on Starting Transfer from the SPBSSL Retained
State in SPI Operating Mode.
17. SPI Multi I/O Bus Controller
20 19 18 17 16
- - - - -
0 0 0 0 0
R R R R R
4 3 2 1 0
- - SPIRE SPIWE SPIE
0 0 0 0 0
R R R/W R/W W
17-17