Rscan0Gerfl - Global Error Flag Register - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.8 RSCAN0GERFL — Global Error Flag Register
Access: Can be read in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 0090
Initial value: 0000 0000
H
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Note 1.
Table 21.22
Bit Position
31 to 29
2
1
0
All flags in the RSCAN0GERFL register are cleared to 0 in global reset mode.
THLES Flag
The THLES flag is set to 1 when any one of the THLELT flags in the RSCAN0THLSTSm register (m
= 0 or 1) is set to 1.
This flag is cleared to 0 when the THLELT flags of all channels are set to 0.
MES Flag
The MES flag is set to 1 when any one of the RFMLT flags in the RSCAN0RFSTSx register (x = 0 to
7) or the CFMLT flags in the RSCAN0CFSTSk register (k = 0 to 5) is set to 1.
This flag is cleared to 0 when all RFMLT flags and CFMLT flags are set to 0.
DEF Flag
The DEF flag is set to 1 when an error has been detected during the DLC check. The program can clear
this flag by writing 0 to this bit.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
28 27 26 25
— — — —
0 0 0 0
R R R R
12 11 10 9
— — — —
0 0 0 0
R R R R
The only effective value for writing to this flag bit is 0, which clears the bit. Otherwise writing to the bit results
in retention of its state.
RSCAN0GERFL register contents
Bit Name Function
Reserved The read value is undefined. The write value should always be 0.
THLES Transmit History Buffer Overflow Status Flag
0: No transmit history buffer overflow has occurred.
1: A transmit history buffer overflow has occurred.
MES FIFO Message Lost Status Flag
0: No FIFO message lost error has occurred.
1: A FIFO message lost error has occurred.
DEF DLC Error Flag
0: No DLC error has occurred.
1: A DLC error has occurred.
24 23 22 21
— — — —
0 0 0 0
R R R R
8 7 6 5
— — — —
0 0 0 0
R R R R
21. CAN Interface
20 19 18 17
— — — —
0 0 0 0
R R R R
4 3 2 1
— — THLES MES
0 0 0 0
R R R R
16
—
0
R
0
DEF
0
1
R/W*
21-39