Operation; Communication Data Format - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.5

Operation

18.5.1

Communication Data Format

2
The I C bus format consists of 8-bit data and 1-bit acknowledge (one frame). After a start condition or
restart condition is issued, the master device sends the slave address and data direction in the first
frame. The specified slave is valid until a stop condition is issued or a new slave is specified by a restart
condition.
Figure 18.3 shows the I
[7-bit address format]
[10-bit address format: Master transmission]
[10-bit address format: Master reception]
Figure 18.3
SDA
SCL
Figure 18.4
S: Start condition. The master device drives the SDA line low from high level while the SCL line is at a high
SLA: Slave address, by which the master device selects a slave device.
R/W#: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from
A: Acknowledge. The receive device drives the SDA line low. (In master transmit mode, the slave device
A#: Not-acknowledge. The receiving device has not returned a response or is not present so the SDA line has
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
2
C bus format, and Figure 18.4 shows the I
S SLA (7 bits) R/W# A DATA (8 bits)
1 7 1 1
S 11110b+SLA(2 bits) W# A SLA (8 bits)
1 7 1 1
S 11110b+SLA(2 bits) W# A SLA (8 bits)
1 7 1 1
2
I C Bus Format
1 to 7 8
S SLA R/W#
2
I C Bus Timing (SLA = 7 Bits)
level.
the master device to the slave device when R/W is 0.
returns acknowledge. In master receive mode, the master device returns acknowledge.)
remained at the high level.
A A/A# P
8 1 1 1
n (n = 1 or more)
A DATA (8 bits)
8 1 8
n (n = 1 or more)
A Sr 11110b+SLA(2 bits)
8 1 1 7
9 1 to 7 8
A Data
18. I²C Bus Interface
2
C bus timing.
n: Number of transfer frames
A A/A# P
1 1 1
R A DATA (8 bits) A
1 1 8 1
n (n = 1 or more)
9 1 to 7 8
A Data
A/A# P
1 1
9
A P
18-45