Input/Output Pins; Register Configuration - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
• Interval: A specific DMA transfer interval can be specified to adjust the bus occupancy.
9.2

Input/Output Pins

Table 9.1 lists the pin configuration. This module has pins for a single channel (CH0) as the external bus use.
Table 9.1 Pin Configuration
Channel Name
0 DMA transfer request
DMA transfer request acknowledge
DMA transfer end
Note 1. For the active level of DACK0 and TEND0, refer to section 8, Bus State Controller.
9.3

Register Configuration

The register configuration is shown in the figure below.
Figure 9.1 Register Configuration
(a) Next Register Set
This register set is used to set the source address, destination address, and transfer byte count of the DMA transaction to
be executed next.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Pin
Name
DREQ0
DACK0
TEND0
Next Register Set
Next0 Register Set
Source Address
1. Load
Destination Address
Transaction Byte
Next1 Register Set
Source Address
Destination Address
Transaction Byte
DMA Registers Set
I/O Function
Input DMA transfer request input from an external device to channel 0
Output DMA transfer request acknowledge output from channel 0 of
this module
Output DMA transfer end output for channel 0 of this module
DMA
Channel
Current Register Set
Source Address
Destination Address
Transaction Byte
Channel Registers Set
Channel Status
Channel Control
Channel Configuration
Channel Interval
Channel Extension
Select
Link Registers Set
Next Link Address
Current Link Address
DMA Control
DMA Status EN
DMA Status ER
DMA Status END
DMA Status TC
DMA Status SUS
9. Direct Memory Access Controller
2. Transfer
9-2