Current Destination Address Register (Crda_N); Current Transaction Byte Register (Crtb_N) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.4.5

Current Destination Address Register (CRDA_n)

This register indicates the DMA transfer destination address of DMA channel n (n = 0 to 15).
The values are loaded from the Next0/1 Register Set in register mode or from the descriptor read data in link mode. You
cannot write to this register set using software.
Bit: 31
Initial value: 0
R/W: R
Bit: 15
0
Initial value:
R/W: R
Initial
Bit Bit Name Value
31 to 0 CRDA All 0
9.4.6

Current Transaction Byte Register (CRTB_n)

This register indicates the total transfer byte count of DMA channel n (n = 0 to 15). The value of this register becomes 0
when the transaction ends.
The values are loaded from the Next0/1 Register Set in register mode or from the descriptor read data in link mode. You
cannot write to this register set using software.
Bit:
31
Initial value:
0
R/W:
R
Bit:
15
0
Initial value:
R/W:
R
Initial
Bit Bit Name Value
31 to 0 CRTB All 0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
0 0 0 0 0
R R R R R
14 13 12 11 10
0 0 0 0 0
R R R R R
R/W Description
R Current Destination Address Register
Indicates the write address of the next DMA transaction.
The value automatically increments during the DMA transaction. (The value is fixed when
1 is set in DAD of the CHCFG_n register.)
The value increments when a write transfer starts.
Read this register after DMA stops (0 is set in EN of the CHSTAT_n register). (Any value
obtained during the DMA operation should be handled as a reference value.)
30 29 28 27 26
0 0 0 0 0
R R R R R
14 13 12 11 10
0 0 0 0 0
R R R R R
R/W Description
R Current Transaction Byte Register
Indicates the remaining transfer byte count of the currently executed DMA transaction.
The value automatically decrements during the DMA transaction.
The value decrements when a write transfer is completed.
Read this register after DMA stops (0 is set in EN of the CHSTAT_n register). (Any value
obtained during the DMA operation should be handled as a reference value.)
25 24 23 22 21
CRDA
0 0 0 0 0
R R R R R
9 8 7 6 5
CRDA
0 0 0 0 0
R R R R R
25 24 23 22 21
CRTB
0 0 0 0 0
R R R R R
9 8 7 6 5
CRTB
0 0 0 0 0
R R R R R
9. Direct Memory Access Controller
20 19 18 17 16
0 0 0 0 0
R R R R R
4 3 2 1 0
0 0 0 0 0
R R R R R
20 19 18 17 16
0 0 0 0 0
R R R R R
4 3 2 1 0
0 0 0 0 0
R R R R R
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