Riicnmr2 - I²C Bus Mode Register 2 - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
18.3.4 RIICnMR2 — I²C Bus Mode Register 2
Access: RIICnMR2 is a 32-bit readable/writable register.
RIICnMR2L and RIICnMR2H are 16-bit readable/writable registers.
RIICnMR2LL, RIICnMR2LH, RIICnMR2HL, and RIICnMR2HH are 8-bit readable/writable registers.
Address: RIICnMR2: <RIICn_base> + 000C
RIICnMR2L: <RIICn_base> + 000C
RIICnMR2LL: <RIICn_base> + 000C
RIICnMR2HH: <RIICn_base> + 000F
Initial Value: 0000 0006
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Table 18.9
Bit Position
31 to 8
7
6 to 4
3
2
1
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
, RIICnMR2H: <RIICn_base> + 000E
H
, RIICnMR2LH: <RIICn_base> + 000D
H
H
This register is initialized by any reset.
H
28 27 26
— — —
0 0 0
R R R
12 11 10
— — —
0 0 0
R R R
RIICnMR2 register contents (1/2)
Bit Name Function
— Reserved
These bits are read as 0. The write value should be 0.
DLCS SDA Output Delay Clock Source Selection
0: The internal reference clock (IIC φ ) is selected as the clock source of the
1: The internal reference clock divided by 2 (IIC φ /2) is selected as the clock
SDDL[2:0] SDA Output Delay Counter
• When RIICnMR2.DLCS = 0 (IIC φ )
b6 b4
0 0 0: No output delay
0 0 1: 1 IIC φ cycle
0 1 0: 2 IIC φ cycles
0 1 1: 3 IIC φ cycles
1 0 0: 4 IIC φ cycles
1 0 1: 5 IIC φ cycles
1 1 0: 6 IIC φ cycles
1 1 1: 7 IIC φ cycles
• When RIICnMR2.DLCS = 1 (IIC φ /2)
b6 b4
0 0 0: No output delay
0 0 1: 1 or 2 IIC φ cycles
0 1 0: 3 or 4 IIC φ cycles
0 1 1: 5 or 6 IIC φ cycles
1 0 0: 7 or 8 IIC φ cycles
— Reserved
This bit is read as 0. The write value should be 0.
TMOH Timeout H Count Control
0: Count is disabled while the SCL line is at a high level.
1: Count is enabled while the SCL line is at a high level.
TMOL Timeout L Count Control
0: Count is disabled while the SCL line is at a low level.
1: Count is enabled while the SCL line is at a low level.
H
H
25 24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
— — DLCS SDDL[2:0]
0 0 0 0
R R R/W R/W
SDA output delay counter.
source of the SDA output delay counter.*
18. I²C Bus Interface
, RIICnMR2HL: <RIICn_base> + 000E
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
— TMOH
0 0 0 1
R/W R/W R R/W
1
,
H
17 16
— —
0 0
R R
1 0
TMOL TMOS
1 0
R/W R/W
18-16