Selection Of Base Clock In Asynchronous Mode - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
Equation 2:
When D = 0.5 and F = 0:
M = (0.5 − 1/(2 × 16)) × 100%
= 46.875%
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
14.6.7

Selection of Base Clock in Asynchronous Mode

In this LSI, when asynchronous mode is selected, the base clock frequency within a bit period can be set to the frequency
16 or 8 times the bit rate by setting the ABCS bit in SCEMR.
Note that, however, if the base clock frequency 8 times the bit rate is used, receive margin is decreased as calculated
using equation 1 in section 14.6.6, Receive Data Sampling Timing and Receive Margin (Asynchronous Mode).
If the desired bit rate can be set simply by setting SCBRR and the CKS[1:0] bits in SCSMR, it is recommended to use the
base clock frequency within a bit period 16 times the bit rate (by setting the ABCS bit in SCEMR to 0). If an internal
clock is selected as a clock source and the SCK pin is not used, the bit rate can be increased without decreasing receive
margin by selecting double-speed mode for the baud rate generator (setting the BGDM bit in SCEMR to 1).
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
14. Serial Communication Interface with FIFO
14-50