Channel Status Register N (Chstat_N) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.4.7

Channel Status Register n (CHSTAT_n)

This register indicates the status of DMA channel n (n = 0 to 15).
Bit:
31
-
Initial value:
0
R/W:
R
Bit:
15
-
0
Initial value:
R/W:
R
Initial
Bit Bit Name Value
31 to 17 — All 0
16 INTMSK 0
15 to 12 — All 0
11 MODE 0
10 DER 0
9 DW 0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - MODE DER
0 0 0 0 0
R R R R R
R/W Description
R Reserved area. Set 0. A read operation results in 0 being read.
R Indicates the temporary mask status of the DMA transfer end interrupt.
1: Masked temporarily
0: Unmasked temporarily
Set condition(s):
• When SETINTMSK (CHCTRL_n) is set to 1
Reset condition(s):
• When CLRINTMSK (CHCTRL_n) is set to 1
• When SWRST (CHCTRL_n) is set to 1
R Reserved area. Set 0. A read operation results in 0 being read.
R DMA Mode
Indicates the DMA mode. It corresponds to the value set in the DMS bit of the CHCFG_n
register.
0: Register mode
1: Link mode
R Descriptor Error
Indicates whether the link valid value of the read descriptor is invalid (LV = 0) (this is not
dependent on the DIM level of the descriptor). If a descriptor error has occurred, the
transfer is stopped but no DMA error interrupt occurs.
0: Descriptor Error not detected
1: Descriptor Error detected
Set condition(s):
• When the LV value loaded with the descriptor in link mode is 0
Reset condition(s):
• When SWRST (CHCTRL_n) is set to 1
R Descriptor WriteBack
Indicates the descriptor writeback status. The bit maintains 1 if a bus error is received
during descriptor writeback.
0: Operation other than writeback is being performed for the header in link mode.
1: (ER = 0)
Writeback is being performed for the header in link mode.
(ER = 1)
A bus error occurs during writeback for the header in link mode.
Set condition(s):
• When header writeback in link mode starts
Reset condition(s):
• When header writeback in link mode ends with an OK response
• When SWRST (CHCTRL_n) is set to 1
25 24 23 22 21
- - - - -
0 0 0 0 0
R R R R R
9 8 7 6 5
DW DL SR TC END
0 0 0 0 0
R R R R R
9. Direct Memory Access Controller
20 19 18 17 16
- - - - INTMSK
0 0 0 0 0
R R R R R
4 3 2 1 0
ER SUS TACT RQST EN
0 0 0 0 0
R R R R R
9-15