Transmit Fifo Data Register (Ssiftdr); Receive Fifo Data Register (Ssifrdr) - Renesas RZ/A Series User Manual

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RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group

Transmit FIFO Data Register (SSIFTDR)

SSIFTDR is a FIFO register consisting of eight stages of 32-bit registers for storing data to be serially transmitted. On

detecting that the transmit data register (SSITDR) is empty, this module transfers the data for transmission written to

SSIFTDR to SSITDR to start serial transmission, which can continue until SSIFTDR becomes empty. SSIFTDR can be

written to by the CPU at any time.

Note that when SSIFTDR is full of transmit data (32 bytes), the next data cannot be written to it. If writing is attempted,

it will be ignored and an overflow occurs.

Initial value:

Initial value:

Not writable while FIFO is receiving data.

SSIFRDR is a FIFO register consisting of eight stages of 32-bit registers for storing serially received data. When four

bytes of data have been received, this module transfers the received data in the receive data register (SSIRDR) to

SSIFRDR to complete reception operation. Reception can continue until 32 bytes of data have been stored to SSIFRDR.

SSIFRDR can be read but cannot be written to by the CPU. Note that when SSIFRDR is read while it does not hold

received data, the value read is undefined and a reception underflow will occur.

After SSIFRDR becomes full of received data, the data received thereafter will be lost and a receive overflow occurs.

Initial value:

Initial value:

R01UH0437EJ0600 Rev.6.00

Jan 29, 2021

19. Serial Sound Interface

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