Rscan0Gcfg - Global Configuration Register - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.5 RSCAN0GCFG — Global Configuration Register
Access: Can be read/written in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 0084
Initial value: 0000 0000
Bit 31 30 29
Initial value 0 0 0
R/W R/W R/W R/W
Bit 15 14 13
TSBTCS[2:0]
0 0 0
Initial value
R/W R/W R/W R/W
Table 21.19
Bit Position
31 to 16
15 to 13
12
11 to 8
7 to 5
4
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
H
H
28 27 26
0 0 0
R/W R/W R/W
12 11 10
TSSS TSP[3:0]
0 0 0
R/W R/W R/W
RSCAN0GCFG register contents (1/2)
Bit Name Function
ITRCP[15:0] Interval Timer Prescaler Set
When these bits are set to M, the pclk is divided by M.
Setting 0000
TSBTCS[2:0] Timestamp Clock Source Select
b15 b14 b13
0
0
0
0
1
1
1
1
TSSS Timestamp Source Select
0: pclk/2*
1: Bit time clock
TSP[3:0] Timestamp Clock Source Division
b11 b10 b9
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Reserved These bits are always read as 0. The write value should always be 0.
DCS CAN Clock Source Select*
0: clkc
1: clk_xincan
25 24 23 22
ITRCP
0 0 0 0
R/W R/W R/W R/W
9 8 7 6
— —
0 0 0 0
R/W R/W R R
is prohibited when the interval timer is in use.
H
0 0: Channel 0 bit time clock
0 1: Channel 1 bit time clock
1 0: Setting prohibited
1 1: Setting prohibited
0 0: Setting prohibited
0 1: Setting prohibited
1 0: Setting prohibited
1 1: Setting prohibited
1
b8
0 0 0: Not divided
0 0 1: Divided by 2
0 1 0: Divided by 4
0 1 1: Divided by 8
1 0 0: Divided by 16
1 0 1: Divided by 32
1 1 0: Divided by 64
1 1 1: Divided by 128
0 0 0: Divided by 256
0 0 1: Divided by 512
0 1 0: Divided by 1024
0 1 1: Divided by 2048
1 0 0: Divided by 4096
1 0 1: Divided by 8192
1 1 0: Divided by 16384
1 1 1: Divided by 32768
2
21. CAN Interface
21 20 19 18
0 0 0 0
R/W R/W R/W R/W
5 4 3 2
— DCS MME DRE
0 0 0 0
R R/W R/W R/W
17 16
0 0
R/W R/W
1 0
DCE TPRI
0 0
R/W R/W
21-32