Sequence Status Register (Spssr); Bit Rate Register (Spbr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
16.3.7

Sequence Status Register (SPSSR)

SPSSR indicates the sequence control status when this module operates in master mode.
Bit Bit Name
7 to 2 ―
1 SPCP1
0 SPCP0
16.3.8

Bit Rate Register (SPBR)

SPBR sets the bit rate in master mode. If the contents of SPBR are changed while the MSTR and SPE bits in the control
register (SPCR) are 1 with the function of this module enabled in master mode, the subsequent operation cannot be
guaranteed.
When this module is used in slave mode, the bit rate depends on the bit rate of the input clock regardless of the settings of
SPBR and BRDV.
The bit rate is determined by combinations of SPBR settings and the bit settings in the BRDV1 and BRDV0 bits in the
command registers (SPCMD0 to SPCMD3). The equation for calculating the bit rate is given below. In the equation, n
denotes an SPBR setting (0, 1, 2, ..., 255), and N denotes a BRDV1 and BRDV0 bit setting (0, 1, 2, 3).
Table 16.3 shows examples of the relationship between the SPBR register and BRDV1 and BRDV0 bit settings.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 7 6 5
⎯ ⎯ ⎯
Initial value: 0 0 0
R/W:
R R R
Initial Value R/W Function
All 0 R Reserved
The write value should always be 0. Otherwise, operation cannot be
guaranteed.
0 R Command Pointer
0 R During sequence control, these bits indicate one of the command
registers 0 to 3 (SPCMD0 to SPCMD3) that is currently pointed to by the
pointer. The relationship between the setting of SPCP1 and SPCP0 and
SPCMD0 to SPCMD3 is shown below.
For the sequence control, see section 16.4.8 (1) (c), Sequence Control.
00: SPCMD0
01: SPCMD1
10: SPCMD2
11: SPCMD3
Bit:
7 6 5
SPR7 SPR6 SPR5
Initial value:
1 1 1
R/W:
R/W R/W R/W
Bit rate =
16. Renesas Serial Peripheral Interface
4 3 2 1
⎯ ⎯ ⎯
SPCP1 SPCP0
0 0 0 0
R R R R
4 3 2 1
SPR4 SPR3 SPR2 SPR1 SPR0
1 1 1 1
R/W R/W R/W R/W R/W
f (P1φ)
2 × (n + 1) × 2
N
0
0
R
0
1
16-11