Rscan0Thlstsm - Transmit History Status Register (M = 0 Or 1) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
21.3.58 RSCAN0THLSTSm — Transmit History Status Register (m = 0 or 1)
Access: Can be read in 8-, 16-, and 32-bit units
Address: <RSCAN0_base> + 0420
Initial value: 0000 0001
Bit 31 30 29
— — —
Initial value 0 0 0
R/W R R R
Bit 15 14 13
— — —
0 0 0
Initial value
R/W R R R
Note 1.
Table 21.77
Bit Position
31 to 13
12 to 8
7 to 4
3
2
1
0
THLMC[4:0] Bits
These bits indicate the number of unread data sets stored in the transmit history buffer.
THLIF Flag
The THLIF flag is set to 1 when the interrupt source specified with the THLIM bit in the
RSCAN0THLCCm register occurs.
This flag is cleared to 0 in channel reset mode or by the program writing 0 to this flag.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
+ (m * 0004 )
H H
H
28 27 26
— — —
0 0 0
R R R
12 11 10
THLMC[4:0]
0 0 0
R R R
The only effective value for writing to this flag bit is 0, which clears the bit. Otherwise writing to the bit results
in retention of its state.
RSCAN0THLSTSm register contents
Bit Name Function
Reserved These bits are always read as 0. The write value should always be 0.
THLMC[4:0] Transmit History Buffer Unread Data Counter
These bits indicate the number of unread data sets stored in the transmit history
buffer.
Reserved These bits are always read as 0. The write value should always be 0.
THLIF Transmit History Interrupt Request Flag
THLELT Transmit History Buffer Overflow Flag
THLFLL Transmit history Buffer Full Status Flag
THLEMP Transmit History Buffer Empty Status Flag
25 24 23 22
— — — —
0 0 0 0
R R R R
9 8 7 6
— —
0 0 0 0
R R R R
0: No transmit history interrupt request is present.
1: A transmit history interrupt request is present.
0: Transmit history buffer overflow has not occurred.
1: Transmit history buffer overflow has occurred.
0: Transmit history buffer is not full.
1: Transmit history buffer is full.
0: Transmit history buffer contains unread data.
1: Transmit history buffer contains no unread data (buffer empty).
21. CAN Interface
21 20 19 18
— — — —
0 0 0 0
R R R R
5 4 3 2
— — THLIF THLELT THLFLL
0 0 0 0
1 1
R R R/W* R/W*
17 16
— —
0 0
R R
1 0
THLEM
P
0 1
R R
21-107