Lsi Internal Bus; Configuration; Operation - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
5.

LSI Internal Bus

5.1 LSI Internal Bus
5.1.1

Configuration

This LSI has two main buses: the north main bus where peripheral modules are connected and the south main bus where
on-chip RAM and external ROM and RAM are connected. Figure 5.1 is a schematic diagram of the internal buses.
This LSI
Cortex-A9
Bus controller
External ROM/RAM
Figure 5.1 Schematic Diagram of LSI Internal Bus
5.1.2

Operation

Cortex-A9 has separate interfaces for the north main bus and south main bus. The addresses assigned to the north main
bus are accessed through the north main bus interface, and those assigned to the south main bus are accessed through the
south main bus interface.
When a bus master connected to the north main bus, except for Cortex-A9, accesses the on-chip RAM or external ROM
or RAM, access is executed through the bus bridge for access from the north main bus to the south main bus. The bus
masters connected to the south main bus cannot access an address assigned to the north main bus. The internal bus of this
LSI operates in little endian.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bus masters
North main bus
Peripheral modules
Bus masters
South main bus
On-chip RAM
5. LSI Internal Bus
Bus bridge
5-1