Serial Data Reception (Except In Block Transfer Mode) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
15.6.7

Serial Data Reception (Except in Block Transfer Mode)

Serial data reception in smart card interface mode is similar to that in serial communications interface mode. Figure
15.33 shows the data retransfer operation in reception mode.
1. If a parity error is detected in receive data, the PER flag in SSR is set to 1. When the RIE bit in SCR is 1 at this time,
an ERI interrupt request is generated. Clear the PER flag in SSR to 0 before the next parity bit is sampled.
2. For a frame in which a parity error is detected, no RXI interrupt is generated.
3. When no parity error is detected, the PER flag in SSR is not set to 1.
4. In this case, data is determined to have been received successfully. When the RIE bit in SCR is 1, an RXI interrupt
request is generated.
Figure 15.34 shows a sample flowchart for serial data reception. All the processing steps are automatically performed
using an RXI interrupt request to activate the DMAC.
In reception, setting the RIE bit in SCR to 1 allows an RXI interrupt request to be generated. The DMAC is activated by
an RXI interrupt request if the RXI interrupt request is specified as a source of DMAC activation beforehand, allowing
transfer of receive data.
If an error occurs during reception and either the ORER or PER flag in SSR is set to 1, a receive error interrupt (ERI)
request is generated. Clear the error flag after the error occurrence. If an error occurs, the DMAC is not activated and
receive data is skipped. Therefore, the number of bytes of receive data specified in the DMAC is transferred.
Even if a parity error occurs and the PER flag in SSR is set to 1 during reception, receive data is transferred to RDR, thus
allowing the data to be read.
Note 1. For operations in block transfer mode, see section 15.3, Operation in Asynchronous Mode.
Ds D0 D1 D2
RXI interrupt signal
SSR.PER flag
Figure 15.33 Data Retransfer Operation in Reception Mode
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
n-th transfer frame
D3 D4 D5 D6 D7 Dp DE
[2]
[1]
15. Serial Communications Interface
Retransfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(n + 1)-th transfer
frame
Ds D0 D1 D2 D3 D4
[4]
[3]
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