Extended Function Control Register (Secr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
15.2.12

Extended Function Control Register (SECR)

b7 b6
— —
0 0
Value after reset:
Bit Symbol Bit Name
b0 — Reserved
b1 CTSE CTS Enable
b7 to b2 — Reserved
Note 1. Writing to this bit is only possible when the RE and TE bits in the SCR are 0 (both serial transmission and reception are
disabled).
SECR is used to select the extension settings in asynchronous and clock-synchronous modes.
CTSE Bit (CTS Enable)
Set this bit to 1 if the CTS control signal is used for control of transmission and reception. The RTS signal is output when
this bit is set to 0. Set this bit to 0 in smart card interface mode.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
b5 b4 b3 b2
— — — — CTSE
0 0 0 0
Description
This bit is read as 0. The write value should be 0.
0: CTS pin function is disabled (RTS output function is enabled).
1: CTS pin function is enabled
These bits are read as 0. The write value should be 0.
b1 b0
—
0 0
15. Serial Communications Interface
R/W
R
1
R/W*
R
15-22