Interrupt Sources; Interrupts In Serial Communications Interface Mode - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
15.8

Interrupt Sources

15.8.1

Interrupts in Serial Communications Interface Mode

Table 15.16 lists interrupt sources in serial communication interface mode. Individual interrupt sources can be enabled
or disabled with the enable bits in SCR.
If the SCR.TIE bit is 1, a TXI interrupt request is generated when data for transmission are transferred from the TDR to
the TSR. A TXI interrupt request can also be generated by setting the SCR.TE bit to 1 after setting the SCR.TIE bit to 1
or by using a single instruction to set the SCR.TE and SCR.TIE bit to 1 at the same time. A TXI interrupt request can
activate the DMAC to handle data transfer.
A TXI interrupt request is not generated by setting the SCR.TE bit to 1 while the setting of the SCR.TIE bit is 0 or by
setting the SCR.TIE bit to 1 while the setting of the SCR.TE bit is 1.*
When new data are not written by the time of transmission of the last bit of the current data for transmission and the
setting of the SCR.TEIE bit is 1, the SSR.TEND flag becomes 1 and a TEI interrupt request is generated. Furthermore,
when the setting of the SCR.TE bit is 1, the SSR.TEND flag retains the value 1 until further data for transmission are
written to the TDR, and setting the SCR.TEIE bit to 1 leads to the generation of a TEI interrupt request.
Writing data to the TDR leads to clearing of the SSR.TEND flag and, after a certain time, discarding of the TEI interrupt
request.
If the SCR.RIE bit is 1, an RXI interrupt request is generated when received data are stored in the RDR. An RXI interrupt
request can activate the DMAC to handle data transfer.
Setting of any from among the ORER, FER, and PER flags in the SSR to 1 while the SCR.RIE bit is 1 leads to the
generation of an ERI interrupt request. An RXI interrupt request is not generated at this time. Clearing all three flags
(ORER, FER, and PER) leads to discarding of the ERI interrupt request.
Note 1. To temporarily prohibit TXI interrupts at the time of transmission of the last of the data and so on when you wish
a new round of transmission to start after handling of the transmission-completed interrupt, control prohibiting
and permitting of the interrupt by using the interrupt request enable bit in the interrupt controller rather than
using the SCR.TIE bit. This can prevent the suppression of TXI interrupt requests in the transfer of new data.
Table 15.16 Interrupt Sources
Name Interrupt Source
ERI Receive error
RXI Receive data full
TXI Transmit data empty
TEI Transmit end
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
15. Serial Communications Interface
1
Interrupt Flag
ORER, FER, or PER
—
—
TEND
DMAC Activation
Not possible
Possible
Possible
Not possible
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